Low Voltage Differential Signaling (LVDS) and Current Mode Logic (CML) standards are two of the most common high-speed data transmission methods used today, and are redefining data transmission at the physical layer interface, and the point-to-point device interface. LVDS and CML are bringing high speeds and low power to these critical interfaces, providing an essential step in meeting the high bandwidth requirements of tomorrow's networking, telecommunications and multimedia applications.
LVDS is a new data interface standard that is defined in the TIA/EIA-644 and the IEEE 1596.3 standards. The TIA/EIA644 standard is also the most common LVDS standard, strictly dictating all of the electrical parameters that must be met by LVDS drivers and receivers. It is essentially a low noise, low power, low amplitude signaling method used for high-speed data transmission of binary data over copper wire. CML is not regulated by standard, but is instead a loose driver output standard based on a particularly simple output protocol. LVDS/CML uses a lower voltage swing than many other transmission standards. Normal digital I/O works with a supply voltage, typically 3.3 volts or 5 volts as a high (binary 1), and 0 volts as a low (binary 0). With LVDS/CML a differential voltage replaces the standard single ended voltage with respect to ground. Standard LVDS (TIA/EIA 644) allows for a differential voltage (VOD) of about 350 mV (247 mV to 454 mV) with a common mode output voltage (VOC) of about 1.2 volts (1.1V to 1.3V) from ground. With the loose CML standard, (VOD) is about 750 mV (700 mV to 800 mV) and the common mode output voltage (VOC) is undefined, as it is supply dependant, for example, about 2.55V to 3.3V from ground for a 3.3V supply, which is VOC=VCC−750 mV/2=VCC−375 mV. This low differential voltage is what delivers higher data transmission speeds and inherently greater bandwidth with lower power consumption. FIG. 1 illustrates typical voltage swings for some of the various transmission standards.
Typically, LVDS/CML can achieve signaling rates as high as 655 megabits per second (Mbps). The ultimate rate and distance of LVDS/CML data transfer is dependent on the attenuation characteristics of the media and the noise coupling to the environment. Generally however, both LVDS and CML work fine for short distances, while LVDS is best suited for greater distances. LVDS also consumes as little as one-eighth the power of RS422 drivers, while CML consumes about 750 mW.
LVDS/CML uses a dual wire (differential) system, running 180 degrees out of phase with each other. This enables noise to travel at the same level as the signal, but common to both wires (common mode), causing the vast majority of the noise to cancel. Since the receivers respond only to differential voltages, they are relatively immune to noise such as common-mode signal reflections. In addition, LVDS emits less electromagnetic interference (EMI) than higher voltage single ended data transmission standards. Because CML is about twice the differential voltage of LVDS, CML is a higher EMI source than LVDS.
LVDS is generally used for point-to-point data transmission over backplane and cable media (the physical layer interfaces), while CML is more often used for point-to-point signaling between devices on a single board, and shorter backplane use. Applications for general purpose LVDS include central office, PBXs, switches, repeaters, and basestations, all of which are in the telecommunications field. In addition, LVDS is used in hubs, routers, and PECL/ECL to LVDS converters in data communications, and other applications such as digital cameras, printers and copiers.
While LVDS addresses the physical layer interface, CML is also rapidly becoming one of the most common standards for high speed point-to-point signaling between devices on a single board, and short backplane uses. Common applications for CML include all major digital systems, for example, ASIC's and DSP's.
Outside the TIA/EIA-644 standard lies multipoint LVDS. Multipoint LVDS supports backplane applications such as proprietary buses and small computer system interfaces or SCSI. SCSI is a high-performance peripheral interface that distributes data independently of the host computer. SCSI is used with devices such as hard disk drives, tape drives, CD-ROMs and scanners.
In addition to general-purpose point-to-point applications and multipoint applications, LVDS has been used for several years as an interface to flat panel displays. As a result, it is used extensively in notebook computers.
Physical layer interfaces are often a critical bottleneck in an application that requires high bandwidths, such as telecommunications and high speed networking. Using a differential signal reduces the system's susceptibility to noise and reduces EMI emissions, as well as delivering high speeds. Thus low voltage differential signaling results in a very cost-effective solution to some of the greatest bandwidth bottlenecks in many transmission applications.
As the need for faster communications and higher performance devices has grown, manufacturers have responded with new higher speed fiber optic technologies and applicable new optical transmission standards.
FIG. 2 shows some of the new Optical Carrier (OC) standards used to specify the speed of fiber optic networks conforming to the Synchronous Optical Network (SONET) standard for connecting fiber optic transmission systems. The table shows the speeds for common OC levels. For example, a high speed transceiver, conforming to OC-24, communicates at a minimum of 1.244 billion bits per second (Gbps).
FIG. 3 illustrates a standard metal cable communicating an analog signal, and a fiber optic cable communicating a digital signal. Fiber optic cables use glass or plastic threads (fibers) to transmit data. A fiber optic cable consists of a bundle of glass or plastic threads, each of which is capable of transmitting messages modulated onto light waves.
Fiber optic cables have several advantages over traditional metal communications lines: Fiber optic cables have a much greater bandwidth than metal cables, and can therefore carry more data. Fiber optic cables are less susceptible than metal cables to interference, are much thinner and lighter than metal wires, and data can be transmitted digitally rather than in an analog fashion.
Fiber optics and the new OC-X standards thus permit data transmission at much higher speeds, but still require the use of the physical layer interface devices such as transceivers and repeaters to receive, convert and transmit the data.
A conventional repeater circuit is illustrated in FIG. 4 and designated at reference numeral 200. The repeater circuit 200 receives a data transmission as a low voltage differential signal at, for example, 200 Mbps and 250 mV to 400 mV P—P signal swing centered at 1.2 Volts. This 1.2 Volt DC offset voltage for the differential signal is called the common mode voltage. This LVDS differential signal 205 is input to a receiver 210 which amplifies and converts the low voltage differential signal to TTL/CMOS single ended (binary) levels 215, which are more easily used by a predrive circuit 220. The predrive circuit 220 further amplifies, may convert to appropriate bias levels, or otherwise prepares the single ended signal 225, which is applied to the driver circuit 230. The driver circuit 230 contains low impedance drive transistors which again convert the data signal back into an LVDS differential signal, which is driven to the output terminals 235 across a resistive load, RLOAD 240. Thereby, a differential input voltage 205 is translated to a differential output voltage 235 and transmitted to a resistive load, RLOAD 240. This data transmission may travel over copper cables, printed circuit board traces or fiber optic cables.
One of the chief technical problems in producing a high speed repeater (e.g., up to 1.36 Gbps operation desired by many telecommunications customers) is meeting the extremely low rise/fall time and jitter requirements necessary for transmission of such fast signals. In most differential transceivers, there is at some point a translation from balanced differential to single ended logic and back to differential output levels. Because of the inherent difference in pull-up and pull-down speeds of differential to single ended translators, pulse skew (duty cycle modulation) and jitter are maximized at this point in the circuit. For this reason, and as discussed, the signal paths of high speed LVDS repeaters are fully balanced differential. Such repeaters are often implemented in Bipolar or BiCMOS processes, and employ all NPN output circuits. Though Bipolar circuits are fast, many DC biasing problems arise in the predrive and common mode correction schemes which are required to support these circuits.
FIG. 5 illustrates a previous generation LVDS driver circuit 245. The driver circuit 245 comprises a current loaded H-Bridge type circuit 250 that uses logic level input signals at IN1 and IN2 (e.g., 225 of FIG. 4) to control the direction of current in the load resistor RLOAD (e.g., 240 of FIG. 4). M1 and M3 are PMOS transistors, while M2 and M4 are NMOS transistors of the H-Bridge type circuit 250. In this configuration, the polarity of the IN1 signal is opposite of IN2, such that when IN1 is high, the M2 and M3 transistors are on, and when IN1 is low, the M1 and M4 transistors are on. This steers the drive output stage currents 11 (255) (e.g., about 3.5 mA) and 12 (260) (e.g., about 3.5 mA) through RLOAD to provide the differential output voltage. Note that in this configuration, half the transistors are on, and half are off at any time as they are used in a switch-mode fashion. Consequently, separate common mode control must be provided indirectly from the H-Bridge to an additional current control element (e.g., I1 (255) via control line 290.
The common mode voltage of the differential output of FIG. 5 is controlled by the operational amplifier (opamp) A1 (265). The common mode is detected at node A 270 by the resistors R1 and R2 which are generally several orders of magnitude larger than RLOAD, and is fed back to the inverting input of the opamp A1 (265). The common mode voltage 270 is compared with a reference voltage VREF (280), which in the case of TIA/EIA-644 compliant systems is set to 1.2 volts, and is generally created by a bandgap reference circuit 285. The output of the opamp A1 (290) is used to adjust the current 11 (255) to adjust the common mode of the output up or down. This conventional circuit has provided years of excellent results in LVDS systems, but can only achieve rise and fall times in the 400 ps range. For high speed repeater systems with transmission rates up to 1.36 Gbps, however, rise times of less than 220 ps under all conditions of temperature, supply voltage and process variation are required to conform to OC-24.
FIG. 6 illustrates a typical response 300 of the first generation LVDS driver circuit at 200 Mbps. FIG. 6 illustrates the differential output signals 310 and 320 (e.g., 235 of FIG. 4) which are seen on each side of RLOAD (e.g., 240 of FIG. 4), and a typical rise/fall time of about 400 ps. Note that the differential output signals 310 and 320 are centered about a common mode voltage of about 1.24 volts, have a signal swing of about 330 mV P—P, and a period of about 10 ns for a frequency of 100 MHz (200 Mbps). Thus, the conventional MOS driver circuit 245 of FIG. 5 is inadequate to provide the rise and fall times required for high speed (e.g., about 1.36 Gbps) data transmission to conform to OC-24.
FIG. 7 illustrates another prior art high speed repeater driver output stage 350 in an H-Bridge type circuit configuration. This circuit employs the high speed NPN devices which make high speed BiCMOS processes attractive to the RF designer. In this case, Q1 and Q2 are driven by a set of low voltage differential predrive signals IN1 and IN2. Q3 and Q4 are driven by a separate set of predrive signals IN3 and IN4. R3 and R4 drop the voltage to the output terminals Y and Z 360 to generally place the common mode voltage at the differential output in the vicinity of 1.2 volts, when operated at IREF 370. Although this circuit is exceedingly fast, providing rise times which easily meet the 220 ps requirements for 1.36 Gbps data transmission, there are several problems which must be overcome by the predrive stage (e.g., 220 of FIG. 4).
The first problem is in the biasing of the predrive signals. NPN devices must be biased in a very narrow range of input voltages in order to stay between the cutoff and saturation regions of operation. At the common mode output levels required by the TIA/EIA644 standard, the level required at IN1 and IN2 must fall in a range of a few hundred millivolts over all conditions of temperature and supply voltage. This type of control is difficult to achieve, and requires a great deal of care on the part of the designer.
The second problem is that of common mode control. The TIA/EIA644 standard calls for common mode output in the range from 1.125 V to 1.375 V. Since this is a fairly tight specification, some kind of control must be provided to assure this level, as in the circuit of FIG. 5. For the circuit of FIG. 7, the common mode control must be built into the predrive circuitry which provides the signals at IN1, IN2, IN3 and IN4. The topology of the driver output stage 350 is such that any control of the common mode is difficult at best, and probably will not meet the stringent requirements of the TIA/EIA644 standard.
FIG. 7A illustrates a prior art standard CML output driver 380, comprising a low-side differential pair with pull-up resistors and a common reference current source. The driver standard accepted by the industry for CML is basically an open collector (or open drain for MOS) differential pair to the output. Q1 and Q2 comprise the transistor differential pair of the CML driver output stage 380, with input signals coming from IN+, and IN−. The circuit is intended to switch current through R1 and R2 depending on the polarity of the inputs at IN+ and IN−.
The CML load is typically purely resistive, and is connected differentially to the supply. R1 & R2 are 50 ohm load resistors that are commonly implemented external to the differential pair. This topology, in addition to being extremely simple and quite fast, also has the advantage of terminating the output media to exactly 50 ohms. Termination in this manner minimizes distortion due to signal reflection. When the reference current (tail current) IREF 390 is set to 15 mA, the output differential voltage between OUT+ and OUT− is:VOUT=15 mA*50 ohms=750 mV. 
Generally, the output protocol is intended to be a differential output that switches somewhere between 700 mV and 800 mV with a fairly high common mode output voltage VCM of:VCM=VCC−750 mV/2, VCM=VCC−375 mV. Outputs of this type are generally not tri-stateable, and there is no standard for short circuit protection or leakage current, etc.
Accordingly, there is a need for a single high bandwidth driver circuit which is able to drive a standard CML load with a CML compatible signal, and a standard LVDS load with an LVDS differential signal conforming to the new OC-24 and TIA/EIA-644 standards, and wherein the driver operates at up to 1.36 Gbps with less than 220 ps rise/fall times, demonstrates a high jitter tolerance with excellent common mode control even at high current loading, while maintaining a simple pre-drive circuit design with a wide common mode range.